| 000 | 01285cam a22003134a 4500 | ||
|---|---|---|---|
| 001 | 13388 | ||
| 003 | BD-DhGUBL | ||
| 005 | 20230210170013.0 | ||
| 008 | 030701s2004 njuad b 001 0 eng | ||
| 010 | _a 2003057671 | ||
| 020 | _a0471441481 (cloth) | ||
| 020 | _a9812531319 | ||
| 040 |
_aDLC _cDLC _dDLC _dBD-DhGUBL |
||
| 042 | _apcc | ||
| 050 | 0 | 0 |
_aTK7885.7 _b.P37 2004 |
| 082 | 0 | 0 |
_a621.392 _222 _bP136d |
| 100 | 1 |
_aPadmanabhan, T. R. _eauthor. |
|
| 245 | 1 | 0 |
_aDesign through Verilog HDL / _cT.R. Padmanabhan, B. Bala Tripura Sundari. |
| 260 |
_aPiscataway, NJ : _bIEEE Press ; _aHoboken, NJ : _bWiley-Interscience, _cc2004. |
||
| 300 |
_axiii, 455 p. : _bill., digras. ; _c25 cm. |
||
| 504 | _aIncludes index and bibliographical references (p. 449-450). | ||
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 650 | 0 |
_aEEE _vSystem analysis. |
|
| 700 | 1 |
_aBala Tripura Sundari, B. _q(Bandaru) _ejoint author. |
|
| 856 | 4 | 2 |
_3Publisher description _uhttp://www.loc.gov/catdir/description/wiley039/2003057671.html |
| 906 |
_a7 _bcbc _corignew _d1 _eocip _f20 _gy-gencatlg |
||
| 942 |
_2ddc _cBK |
||
| 999 |
_c4545 _d4545 |
||